1. Field of the Invention
This invention relates generally to computing methods and systems that facilitate electronic design automation of integrated circuitry. More specifically this invention is related to methods and apparatus that adjust resistance and capacitance parameters in a library database containing a description of circuits and constraints of an integrated circuit fabricating process. The library database is used in a physical synthesis program module of a design automation system.
2. Description of Related Art
The structure of the methods and systems used to design and prepare an integrated circuit for fabrication is well known in the art. Referring to FIG. 1, the integrated circuit design begins with creation (Box 100) of a high-level circuit spefication. The high-level circuit specification details the function of the integrated circuit, and the constraints of the integrated circuit such as physical size, voltage levels, current levels, power dissipation, frequency, and environmental factors (temperature, etc.). The circuit function is translated to a logic design written in a hardware description language such as VHDL (Very High Speed Integrated Circuit Hardware Description Language) or Verilog Hardware Description Language.
Generally, the structure of the integrated circuit is in register transfer language (RTL) and the hardware descriptor language is structured as the RTL code (Box 105). The RTL code (Box 105) is transferred to a program system that generates or synthesizes (Box 110) a circuit or gate level design from the hardware description of the integrated circuit. The logic synthesis (Box 110) provides the initial description of the physical structure that the integrated circuit is to have. The logic synthesis (Box 110) in what is termed timing driven design performs a rough estimate of the delays of each circuit of the design including the intrinsic delay of each circuit and an estimate of the timing delays caused by the interconnecting wiring. The logic synthesis (Box 110) employs a wire load model (WLM) (Box 115) to provide an estimate of the timing delays that result from the interconnecting wiring.
The wire load model is a statistical model that provides an estimate of wiring length for a path based on the type of path (long path, short path, control logic, functional logic, array data path, or array control path) and some historic statistics for the particular circuit path types. Further, it is known that certain functions will be grouped and therefore circuit paths within a function have one estimated length while inter-function circuit paths will have a different length (longer). Based on the statistical data and certain constraints and estimates, the logic synthesizer can provide a rough prediction of the timing delays for the circuit paths of an integrated circuit.
Once the logic synthesis (Box 110) is completed, the circuits are then placed (Box 120) based on the constraints developed in the design specification (Box 100) and during the logic synthesis (Box 110). After the circuits are placed (Box 120), the interconnecting wiring is routed (Box 125). This defines the actual structure of each segment of the printed circuit wiring of the integrated circuit. The wiring is generally placed on multiple levels and is routed in horizontal and vertical directions depending on the level of the wire routing.
The completed wire routing description is used to extract (Box 130) the resistance and capacitance values for each segment of all the wiring interconnections of the integrated circuit. This is the first opportunity for a true statistical timing analysis to determine the performance of the integrated circuit. The resistance and capacitance of each segment of the interconnecting wiring is generally determined employing a three-dimensional solver. The three dimensional solver calculates the resistance of the segments based on the cross-sectional area and length of each segment and the resistivity (xcfx81) of the interconnecting wiring segments. The three dimensional solver calculates the capacitance based on the surface area of the wiring, the distance to the adjoining wiring segments or the semiconductor substrate, and the dielectric constant (xcex5) of the intervening insulator. These calculated resistances and capacitances are relatively accurate and allow a timing analysis (Box 135) that predicts the performance of the integrated circuit precisely within the bounds of the process variations. The design of the integrated circuit is evaluated (Box 140) to establish if the design complies with the design specification. If the design specification is not met the design is appropriately modified (Box 145) and the process repeated. If the design complies with the specification, the design is then fabricated (Box 150)
It is well known in the art that, as the lithography of the semiconductor processing has improved to allow minimum feature size to decrease from 0.5 xcexcm to 0.25 xcexcm to approaching 0.18 xcexcm and event to 0.1 xcexcm, the proportion of the delay of a circuit path that is attributable to the interconnections has increased. The increase has been from approximately 20% at 0.5 xcexcm to approximately 45% at 0.25 xcexcm to approximately 60% at 0.18 xcexcm and smaller. Further, as shown in FIG. 4a, the error in the capacitance used by the WLM model to estimate the path delay at the logical synthesis versus the actual capacitance as determined during the resistance and capacitance extraction (Box 130) is greater than +/xe2x88x9220% (region A) for more than 50% of the paths of the integrated circuit. When the timing delay that resulted from the interconnections was a smaller proportion of the total path delay, the error had less an impact than when the interconnections become the dominant component of the total path delay.
Logical synthesis provided a logical design with only rudimentary consideration to the physical structure of the integrated circuit To refine the estimate of timing delay and its impact on performance of the integrated circuit logical synthesis, logical synthesis was replaced with physical synthesis. Refer now to FIG. 2 for a discussion of an electronic design automation process. The design specification is created essentially as described above, with creation (Box 100) of a high-level circuit specification. The high-level circuit specification details the function of the integrated circuit, and the constraints of the integrated circuit such as physical size, voltage levels, current levels, power dissipation, frequency, and environmental factors (temperature, etc.). The high-level circuit specification is then translated (Box 105) to the Register Transfer Language Coding. The RTL coding (Box 105) is not complete as in the Electronic Design process of FIG. 1. Newly designed circuit functions are described functionally, without the detailed RTL coding. Current integrated circuit designs further have predesigned circuit functions such as memory arrays, microprocessors, etc.
The integrated circuit design is partitioned (Box 200) to allocate the functional units of the integrated circuit design to unique physical areas of the substrate onto which the integrated circuit is to be fabricated. The circuit specification contains certain performance and timing criteria that are to be achieved by the integrated circuit. These timing and performance constraints are then budgeted (Box 205) and allotted to the appropriate functional units of the integrated circuit design.
The RTL coding (Box 105) is now transferred to a physical synthesizer to create the initial schematic description of the integrated circuit. Physical synthesis (Box 210), as described in xe2x80x9cPhysical Synthesis: Design Tools and Flows for Sub-Micron, System-On-a-Chip Design Implementation,xe2x80x9d Synopsis, Inc., Mountain View Calif., May 1999, brings key physical functions into the front-end process that allow an integrated circuit design to have the impact of the physical implementation of the design considered earlier in the process. Many of these predesigned circuit functions are completely designed to the final wiring levels and only need to have interconnections made to other functions on the integrated circuit. Consequently, the timing analysis for these predesigned circuits is complete and well understood.
Physical Synthesis (Box 210) consists of three major components, Black Box Planning (Box 212), RTL Planning (Box 213), and Gate Level Planning (Box 214). Black Box Planning (Box 212). Black Box Planning actually occurs before the RTL code for those circuits that are being designed specifically for the integrated circuit. The inputs to Black Box Planning are:
A netlist defining the interconnections of the major functions of the integrated circuit.
Timing and physical models for predesign circuits.
The timing design constraints for each of the major functions.
The input/output (I/O) placement specification for the whole integrated circuit and for the major functions, particularly the predesigned circuit function.
Black Box Planning initially creates a floorplan defining the tentative arrangement of the integrated circuit on a semiconductor substrate. The size and timing of the predesigned circuit functions is known, but the timing and area of the newly designed circuit functions is estimated. Previous experience is used to estimate the block size and timing to create xe2x80x9cblack boxesxe2x80x9d defining the newly designed circuit functions. Later, when the actual RTL code is written for each of the newly designed function, the user-estimated black box models are replaced with gate-level netlists generated by synthesis tools.
Next, power bus planning is performed in order to account for the metal resources that these busses will consume. These busses bring power from the I/O ring into the areas of the predesigned circuit functions and the newly designed circuit functions. Allocating area for these power busses early results in a more accurate view of the design. The integrated circuit""s external I/O cells are then placed, usually based on a specification from the board-level design stage. The I/O structures of newly designed circuit functions are automatically assigned and are optimally placed based on connections between various functions of the integrated circuit and the timing constraints. A quick, coarse routing of the interconnections between the circuit functions is performed by a global router. The global router routes each and every net in the design on a coarse grid in order to estimate the interconnect quickly. The global router takes into account the blockages caused by power busses, pre-routed signals, and metal used to connect nets within the circuit functions.
The design is then analyzed for timing and routing congestion and modifications are made to reduce gross timing errors and remove areas that are overly congested for routing. Modifications are done to the locations of the circuit functions on the semiconductor substrate, to the shape of the newly designed circuit functions, and to the placement of the I/O structures of the newly designed circuit functions.
When severe timing and/or congestion problems are found, the design is re-partitioned to minimize the timing and routing problems. The newly designed circuit functions may be divided into other physical units to insure that any congestion of the wiring or timing constraints are minimized.
The outputs of Black Box Planning are an initial floorplan, an estimate of the power consumption and distribution of the integrated circuit, the timing and power constraints of the newly designed circuit function, and an initial routing of the interconnections between the circuit functions.
The RTL Planning stage (Box 213) is similar to Black Box Planning (Box 212) except that the estimated timing and physical models for the newly designed circuit functions are replaced with gate-level netlists generated by a logical synthesis tool or program. The synthesis constraints created in the black box stage are used to quickly create gate-level netlists using a logical synthesis tool. The synthesis tool very quickly creates the gate-level netlist, but in the process, sacrifices some accuracy in return for high performance. The black boxes used for the newly designed circuit functions are replaced with the newly generated netlists. The gates in these estimated netlists are quickly placed to better estimate the timing and area of each of the newly designed circuit functions. Based on these more accurate representations of the newly designed circuit functions, minor refinements are made to the floorplan, I/O structures of newly designed circuit functions, circuit function interconnection routing, and design budgets. In addition, custom ware load models are created for each newly designed circuit function, based on the quick placement of the estimated netlists. The outputs of RTL Planning are custom wire load models for each of the newly designed circuit functions; a refined floorplan, I/O structure locations, Interconnection routing of the circuit functions, and power planning; and refined design budgets for each of the circuit functions.
A gate-level implementation is of the integrated circuit is performed during the Gate-Level Planning stage (Box 214). Each newly designed circuit function is independently synthesized (in parallel) using the custom wire load models and design budgets created and refined in previous design steps (Boxes 212 and 213). The final, detailed cell placement and global routing is performed on each newly designed circuit function (in parallel). Clock trees are synthesized for each newly designed circuit function and for the entire chip. Each newly designed circuit function and the entire integrated circuit are analyzed to insure that timing constraints and goals are achieved and congestion is minimized.
After the analysis during the Gate-level Planning stage (Box 214) any minor modifications of placement are made (Box 220) to adjust any error found in the analysis. A final routing (Box 225) of the interconnections of the circuit functions is performed, generally repair any antennas (modification of the wire to gate or diode area ratio) found in the analysis. Again the resistance and capacitance is extracted (Box 130) by the three-dimensional solver to calculate the exact resistance and capacitance of each segment of the interconnections. A final timing analysis (Box 135) is performed using the extracted (Box 130) resistances and capacitances. The results are analyzed (Box 140) to insure that the physical design of the integrated circuit will perform as required by the design specification. If there are still noncompliances with the design specification the design is modified (Box 145) and the electronic design automation system is reiterated until the design is in compliance. The design is then fabricated (Box 150).
One of the advantages of the physical synthesis is that the timing analysis is now based on a preliminary routing of the interconnections of the circuit functions. A library (Box 215 contains the descriptions of the resistance and capacitance of the various interconnection segments. The timing analysis now is based on the preliminary routing information with a more accurate estimate of the resistance and capacitance for the interconnection segments. However, since the resistance and capacitance of the routed interconnections of the integrated circuit are based on library descriptions rather than actual calculations there are still deviations in the estimates from the actual calculation determined by the three-dimensional solver program.
A representative illustration of two different integrated circuit designs 400 and 450 is shown in FIG. 4b. In the first instance 400 approximately 40% of the paths of the integrated circuit have a capacitance error less than +/xe2x88x9220% for the estimate employed by the description from the library 215 of FIG. 2 versus the actual calculation from the resistance capacitance extraction (Box 130) of FIG. 2. In the second instance 450 approximately 51% of the paths of the integrated circuit have a capacitance error less than +/xe2x88x9220% (Region A) for the estimate employed by the description from the library 215 of FIG. 2 versus the actual calculation from the resistance capacitance extraction (Box 130) of FIG. 2. Further, nearly all the capacitance errors for the paths for the first design 400 and second design 450 fall in the range of +/xe2x88x9260%. This is a significantly better estimate than is accomplished using the wire load model of FIG. 4a. As the minimum feature size has decreased from 0.6 xcexcm to 0.25 xcexcm, the proportion of the path delay through the circuit functions for the interconnections has increased from 20% to 40%. Thus the overall effect of the improvement of the estimate is in effect nullified, since the impact of the interconnections on the path delay is increased.
Further, an even more accurate estimate of the resistance and capacitance of the interconnections of the integrated circuit is required during the physical synthesis, as the minimum feature size is again decreased to approach 0.18 xcexcm. The effect of the resistance and capacitance of the interconnection on the path delay will increase to approach 60% of the total delay. This will increase the impact of the errors between the estimates created by the library 215 versus the actual calculated resistances and capacitances.
Electronic Design Automation tools are well known in the art and are marketed by corporations such as Synopsis, Inc and Avant!, Inc. of Fremont Calif. Avant!, Inc. markets circuit placement and interconnection routing programs under the trade names Apollo and Astro. The Apollo program set provides timing analysis using the library of the resistances and capacitances as described in FIG. 2. Apollo further markets a resistance and capacitance extraction tool under the tradename Star-RCXT, which provides a three-dimensional calculation of resistance and capacitance as shown in FIGS. 1 and 2. Further, Avant! markets a program product under the tradename Raphael that provide the field solver necessary to calculate the resistance and of interconnections and to evaluate current density of interconnections and complex electrical and thermal evaluations.
U.S. Pat. No. 5,629,860 (Jones, et al.) provides a method for determining timing delays associated with the placement of circuit function and routing of the interconnections of an integrated circuit. In particular, Jones et al determines the area of each region wherein a region includes a group or subgroup of circuit functions for use in designing an integrated circuit. Once the area for each region is obtained, substantially more accurate and more design specific wire load model and net parasitics can be obtained. The wire load models or net parasitics can then be supplied to other CAE tools to create a modified netlist. Moreover, the present invention provides a process, which allows the user to account for the resistance and capacitance effects of the interconnections of the circuit functions on a hierarchical block basis. The process to account for the resistance and capacitance effects thus improves the accuracy of the wire placement and routing delay estimate while preserving the performance benefits of a traditional simplified equation.
U.S. Pat. No. 5,815,406 (Golla, et al.) describes a method and system for designing a circuit using the resistance and capacitance and timing weighting of the interconnections of the integrated circuit. The method includes the steps of identifying the circuit functions that are connected by interconnecting wiring and assigning weights to the interconnections in proportion to timing and resistive and capacitive (RC) effects of the interconnection. In the preferred embodiment, the weights are used by a conventional placement program to obtain the final placements.
U.S. Pat. No. 6,080,201 (Hojat, et al.) teaches a method for improving timing convergence in computer aided semiconductor circuit design. In one particular version of the invention, the method includes the steps of generating a behavioral model of a desired semiconductor circuit. The behavioral model includes timing constraints for individual paths in the circuit. The behavioral model is synthesized to produce a netlist, which represents an implementation of the desired semiconductor circuit mapped to a specific semiconductor technology. The netlist includes a list of components in the circuit and a list of interconnecting wires, which connect the components in the circuit. The synthesizing includes performing a timing analysis on the implementation so that the paths in the circuit represented by the netlist meet the timing constraints, the timing analysis being performed using estimated wire lengths for the nets. Next, the components in the netlist are placed into an image representing a predefined area of the semiconductor substrate. During this step, actual wire lengths are determined for the nets in the netlist. Given the actual wire lengths, the steps of synthesizing and placing are then repeated until timing convergence is achieved. Each time the step of synthesizing is repeated, the actual wire lengths from the step of placing are substituted for the estimated wire lengths. Finally, the circuit is routed to produce the final design data.
U.S. Pat. No. 6,145,117 (Eng) discusses creating optimized physical implementations of integrated circuits from high-level descriptions of electronic design using placement-based information. The electronic design automation system provides optimization of RTL models of integrated circuits, to produce detailed constraints and data precisely defining the requirements for the back-end flows leading to design fabrication. The system takes an RTL model of an electronic design and maps it into an efficient, high-level hierarchical representation of the hardware implementation of the design. The hardware representation is partitioned into functional partitions, and a fully characterized performance envelope is created for a range of feasible implementations for each of the partitions, using accurate placement based wire load models. Chip-level optimization selects and refines physical implementations of the partitions to produce compacted, globally routed floorplans. Chip-level optimization iteratively invokes re-partitioning passes to refine the partitions and to recompute the feasible implementations. In this fashion, a multiple-pass process converges on an optimal selection of physical implementations for all partitions for the entire integrated circuit that meet minimum timing requirements and other design goals. The system outputs specific control and data files which thoroughly define the implementation details of the design through the entire back-end flow process, thereby guaranteeing that the fabricated design meets all design goals without costly and time consuming design iterations.
U.S. Pat. No. 6,189,131 (Graef, et al.) explains a method for selecting and synthesizing metal interconnect wires in integrated circuits. The method assigns signals to specific metal layers through the use of interconnect wire load models that are metal layer dependent. The method allows synthesis and layout tools to route signal wires on select metal layers at an early stage in the design process. A technology library is used in designing integrated circuits. In addition to traditional library components such as logic gate information, the technology library includes routing wire load models that are metal layer dependent. The wire load information reflects the electrical properties of signal wires formed on different metal layers, and provides more accurate timing estimates than generic wire delay values. The additional information influences the delay calculations of the synthesis process in such a way that the delay a signal encounters on a specific metal layer can be approximated very closely. A wire-metal layer attribute file is compiled by the synthesis process. The wire-metal layer attribute file output constrains layout tools to route individual signals on specific metal layers. Altematively, the layout tool can utilize the wire-metal layer attribute file to determine a set of acceptable routing layers, allowing an optimal route for a signal to be chosen in relation to the requirements of other signals.
U.S. Pat. No. 6,279,142 (Bowen, et al.) provides a method of on-chip interconnect design in an integrated circuit (IC). Fast circuit simulations of each interconnection of the circuit functions constituting the integrated circuit are performed for noise margin and slew rate analysis. A resistor/capacitor (RC) network for each net is generated from net lengths, and assignments of parasitic cross-coupling capacitances and shunt capacitances derived from three-dimensional field solver evaluations of pre-routing phase estimated wire geometries. If the noise margin and slew rate criteria are not satisfied for the net under simulation, the simulations are iterated, with a new wire geometry selected between iterations, until the criteria are satisfied. Each net is tagged with a wire geometry that satisfies noise margin and slew rate requirements, which can then be passed to a routing tool.
An object of this invention is to provide a method and system for the design of an electronic device that adjusts the resistance and capacitance values employed in preliminary timing analysis during physical synthesis of the electronic device.
To accomplish at least this object a method for designing an electronic device begins by creating a preliminary description of the electronic device including constraints to be employed for the design. A physical synthesis of the preliminary description of the electronic device is performed to form a listing of component circuits of the electronic device including a listing of interconnections of the electronic devices. The physical synthesis uses resistance and capacitance unit values to determine the listing of the component circuits.
The resistance and capacitance unit values are calibrated by preliminarily placing the initially synthesized component circuits to create a listing describing physical locations of the component circuits within the electronic device. A preliminary routing of the interconnections is performed to create a listing describing a network of physical wire segments that form each interconnection of the component circuits. A timing analysis of the electronic device determines delay created by the component circuit and the networks of physical wire segments.
The time delay resulting from the physical interconnects is extracted from the timing analysis of the electronic device and from the timing estimate performed during the physical synthesis. The time delay of the physical interconnection from the timing analysis and the timing estimate performed during the physical synthesis is then compared. The resistance and capacitance unit values used during the timing synthesis are then adjusted and the above calibration process is repeated until the physical interconnect delay and the estimated interconnect delay are correlated.
A final physical synthesis is executed and the component circuits are placed to create a listing describing physical locations of the component circuits within the electronic device. A final routing of the interconnections is preformed to create a listing describing a network of physical wire segments that form each interconnection of the component circuits, eliminating any antenna or extra interconnection segments created in previous iterations of the routing of the interconnections. The design of the electronic device is verified to insure that it adheres to the preliminary description of the electronic device and then the design transferred for fabrication.
The preliminary description of the electronic device is either in a hardware descriptor language, a gate level netlist having a description of the component circuits and the interconnections between the component circuits, or a description of the location of the component circuits with descriptions of the interconnections between the component circuits.